ESPHome  2024.11.1
wk_reg_def.h
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1 #pragma once
6 
7 namespace esphome {
8 namespace weikai {
9 
13 
19 
32 constexpr uint8_t WKREG_GENA = 0x00;
34 constexpr uint8_t GENA_C4EN = 1 << 3;
36 constexpr uint8_t GENA_C3EN = 1 << 2;
38 constexpr uint8_t GENA_C2EN = 1 << 1;
40 constexpr uint8_t GENA_C1EN = 1 << 0;
41 
54 constexpr uint8_t WKREG_GRST = 0x01;
56 constexpr uint8_t GRST_C4RST = 1 << 3;
58 constexpr uint8_t GRST_C3RST = 1 << 2;
60 constexpr uint8_t GRST_C2RST = 1 << 1;
62 constexpr uint8_t GRST_C1RST = 1 << 0;
63 
65 constexpr uint8_t WKREG_GMUT = 0x02;
66 
68 constexpr uint8_t WKREG_GIER = 0x10;
69 
71 constexpr uint8_t WKREG_GIFR = 0x11;
72 
85 constexpr uint8_t WKREG_GPDIR = 0x21;
86 
99 constexpr uint8_t WKREG_GPDAT = 0x31;
100 
108 
114 
127 constexpr uint8_t WKREG_SPAGE = 0x03;
128 
141 constexpr uint8_t WKREG_SCR = 0x04;
143 constexpr uint8_t SCR_TXEN = 1 << 1;
145 constexpr uint8_t SCR_RXEN = 1 << 0;
146 
159 constexpr uint8_t WKREG_LCR = 0x05;
161 constexpr uint8_t LCR_PAEN = 1 << 3;
163 constexpr uint8_t LCR_PAR_F0 = 0 << 1;
165 constexpr uint8_t LCR_PAR_ODD = 1 << 1;
167 constexpr uint8_t LCR_PAR_EVEN = 2 << 1;
169 constexpr uint8_t LCR_PAR_F1 = 3 << 1;
171 constexpr uint8_t LCR_STPL = 1 << 0;
172 
185 constexpr uint8_t WKREG_FCR = 0x06;
187 constexpr uint8_t FCR_TFEN = 1 << 3;
189 constexpr uint8_t FCR_RFEN = 1 << 2;
191 constexpr uint8_t FCR_TFRST = 1 << 1;
193 constexpr uint8_t FCR_RFRST = 1 << 0;
194 
196 constexpr uint8_t WKREG_SIER = 0x07;
197 
199 constexpr uint8_t WKREG_SIFR = 0x08;
200 
209 constexpr uint8_t WKREG_TFCNT = 0x09;
210 
219 constexpr uint8_t WKREG_RFCNT = 0x0A;
220 
241 constexpr uint8_t WKREG_FSR = 0x0B;
243 constexpr uint8_t FSR_RFOE = 1 << 7;
245 constexpr uint8_t FSR_RFLB = 1 << 6;
247 constexpr uint8_t FSR_RFFE = 1 << 5;
249 constexpr uint8_t FSR_RFPE = 1 << 4;
251 constexpr uint8_t FSR_RFDAT = 1 << 3;
253 constexpr uint8_t FSR_TFDAT = 1 << 2;
255 constexpr uint8_t FSR_TFFULL = 1 << 1;
257 constexpr uint8_t FSR_TBUSY = 1 << 0;
258 
260 constexpr uint8_t WKREG_LSR = 0x0C;
261 
263 constexpr uint8_t WKREG_FDAT = 0x0D;
264 
271 
280 constexpr uint8_t WKREG_BRH = 0x04;
281 
290 constexpr uint8_t WKREG_BRL = 0x05;
291 
293 constexpr uint8_t WKREG_BRD = 0x06;
294 
296 constexpr uint8_t WKREG_RFI = 0x07;
297 
299 constexpr uint8_t WKREG_TFI = 0x08;
300 
303 } // namespace weikai
304 } // namespace esphome
constexpr uint8_t GRST_C2RST
Channel 2 soft reset (0: not reset, 1: reset)
Definition: wk_reg_def.h:60
constexpr uint8_t LCR_PAR_ODD
Parity odd.
Definition: wk_reg_def.h:165
constexpr uint8_t WKREG_SCR
Serial Control Register - c0/c1 0100.
Definition: wk_reg_def.h:141
constexpr uint8_t WKREG_FDAT
FIFO Data Register (not used - does not seems to work)
Definition: wk_reg_def.h:263
constexpr uint8_t FCR_TFRST
Transmitter FIFO reset.
Definition: wk_reg_def.h:191
constexpr uint8_t GRST_C4RST
Channel 4 soft reset (0: not reset, 1: reset)
Definition: wk_reg_def.h:56
constexpr uint8_t WKREG_GENA
Global Control Register - 00 0000.
Definition: wk_reg_def.h:32
constexpr uint8_t WKREG_GIER
Global interrupt register (not used) - 01 0000.
Definition: wk_reg_def.h:68
constexpr uint8_t LCR_PAR_F0
Parity force 0.
Definition: wk_reg_def.h:163
constexpr uint8_t WKREG_BRL
Baud rate configuration register: low byte - c0/c1 0101.
Definition: wk_reg_def.h:290
constexpr uint8_t FSR_TBUSY
Transmitter busy (0 nothing to transmit, 1: transmitter busy sending)
Definition: wk_reg_def.h:257
constexpr uint8_t WKREG_GRST
Global Reset Register - 00 0001.
Definition: wk_reg_def.h:54
constexpr uint8_t FSR_RFDAT
Receiver FIFO count (0: empty, 1: not empty)
Definition: wk_reg_def.h:251
constexpr uint8_t WKREG_BRH
Baud rate configuration register: high byte - c0/c1 0100.
Definition: wk_reg_def.h:280
constexpr uint8_t GENA_C2EN
Channel 2 enable clock (0: disable, 1: enable)
Definition: wk_reg_def.h:38
constexpr uint8_t FSR_TFFULL
Transmitter FIFO full (0: not full, 1: full)
Definition: wk_reg_def.h:255
constexpr uint8_t LCR_PAEN
Parity enable (0: no check, 1: check)
Definition: wk_reg_def.h:161
constexpr uint8_t WKREG_FCR
FIFO Control Register - c0/c1 0110.
Definition: wk_reg_def.h:185
constexpr uint8_t WKREG_FSR
FIFO Status Register - c0/c1 1011.
Definition: wk_reg_def.h:241
constexpr uint8_t WKREG_SIFR
Serial Interrupt Flag Register (not used) - c0/c1 1000.
Definition: wk_reg_def.h:199
constexpr uint8_t SCR_TXEN
transmission control (0: enable, 1: disable)
Definition: wk_reg_def.h:143
constexpr uint8_t FSR_RFLB
Receiver FIFO Line Break (0: no LB, 1: LB)
Definition: wk_reg_def.h:245
constexpr uint8_t FSR_TFDAT
Transmitter FIFO count (0: empty, 1: not empty)
Definition: wk_reg_def.h:253
constexpr uint8_t FSR_RFPE
Receiver Parity Error (0: no PE, 1: PE)
Definition: wk_reg_def.h:249
constexpr uint8_t WKREG_GMUT
Global Master channel control register (not used) - 000010.
Definition: wk_reg_def.h:65
constexpr uint8_t LCR_STPL
Stop length (0: 1 bit, 1: 2 bits)
Definition: wk_reg_def.h:171
constexpr uint8_t WKREG_BRD
Baud rate configuration register decimal part - c0/c1 0110.
Definition: wk_reg_def.h:293
constexpr uint8_t WKREG_SIER
Serial Interrupt Enable Register (not used) - c0/c1 0111.
Definition: wk_reg_def.h:196
constexpr uint8_t LCR_PAR_EVEN
Parity even.
Definition: wk_reg_def.h:167
constexpr uint8_t FCR_RFEN
Receiver FIFO enable.
Definition: wk_reg_def.h:189
constexpr uint8_t WKREG_GIFR
Global interrupt flag register (not used) 01 0001.
Definition: wk_reg_def.h:71
constexpr uint8_t FSR_RFOE
Receiver FIFO Overflow Error (0: no OE, 1: OE)
Definition: wk_reg_def.h:243
constexpr uint8_t GENA_C3EN
Channel 3 enable clock (0: disable, 1: enable)
Definition: wk_reg_def.h:36
constexpr uint8_t WKREG_GPDAT
Global GPIO data register - 11 0001.
Definition: wk_reg_def.h:99
constexpr uint8_t FCR_TFEN
Transmitter FIFO enable.
Definition: wk_reg_def.h:187
constexpr uint8_t WKREG_RFCNT
Receiver FIFO count - c0/c1 1010.
Definition: wk_reg_def.h:219
constexpr uint8_t GRST_C1RST
Channel 1 soft reset (0: not reset, 1: reset)
Definition: wk_reg_def.h:62
constexpr uint8_t WKREG_TFI
Transmit FIFO interrupt trigger configuration (not used) - c0/c1 1000.
Definition: wk_reg_def.h:299
constexpr uint8_t SCR_RXEN
receiving control (0: enable, 1: disable)
Definition: wk_reg_def.h:145
constexpr uint8_t WKREG_LSR
Line Status Register (not used - using FIFO)
Definition: wk_reg_def.h:260
constexpr uint8_t GRST_C3RST
Channel 3 soft reset (0: not reset, 1: reset)
Definition: wk_reg_def.h:58
constexpr uint8_t WKREG_TFCNT
Transmitter FIFO Count - c0/c1 1001.
Definition: wk_reg_def.h:209
Implementation of SPI Controller mode.
Definition: a01nyub.cpp:7
constexpr uint8_t FCR_RFRST
Receiver FIFO reset.
Definition: wk_reg_def.h:193
constexpr uint8_t WKREG_SPAGE
Global Page register c0/c1 0011.
Definition: wk_reg_def.h:127
constexpr uint8_t WKREG_RFI
Receive FIFO Interrupt trigger configuration (not used) - c0/c1 0111.
Definition: wk_reg_def.h:296
constexpr uint8_t WKREG_GPDIR
Global GPIO direction register - 10 0001.
Definition: wk_reg_def.h:85
constexpr uint8_t GENA_C1EN
Channel 1 enable clock (0: disable, 1: enable)
Definition: wk_reg_def.h:40
constexpr uint8_t LCR_PAR_F1
Parity force 1.
Definition: wk_reg_def.h:169
constexpr uint8_t FSR_RFFE
Receiver FIFO Frame Error (0: no FE, 1: FE)
Definition: wk_reg_def.h:247
constexpr uint8_t GENA_C4EN
Channel 4 enable clock (0: disable, 1: enable)
Definition: wk_reg_def.h:34
constexpr uint8_t WKREG_LCR
Line Configuration Register - c0/c1 0101.
Definition: wk_reg_def.h:159