constexpr uint8_t GRST_C2RST
Channel 2 soft reset (0: not reset, 1: reset)
constexpr uint8_t LCR_PAR_ODD
Parity odd.
constexpr uint8_t WKREG_SCR
Serial Control Register - c0/c1 0100.
constexpr uint8_t WKREG_FDAT
FIFO Data Register (not used - does not seems to work)
constexpr uint8_t FCR_TFRST
Transmitter FIFO reset.
constexpr uint8_t GRST_C4RST
Channel 4 soft reset (0: not reset, 1: reset)
constexpr uint8_t WKREG_GENA
Global Control Register - 00 0000.
constexpr uint8_t WKREG_GIER
Global interrupt register (not used) - 01 0000.
constexpr uint8_t LCR_PAR_F0
Parity force 0.
constexpr uint8_t WKREG_BRL
Baud rate configuration register: low byte - c0/c1 0101.
constexpr uint8_t FSR_TBUSY
Transmitter busy (0 nothing to transmit, 1: transmitter busy sending)
constexpr uint8_t WKREG_GRST
Global Reset Register - 00 0001.
constexpr uint8_t FSR_RFDAT
Receiver FIFO count (0: empty, 1: not empty)
constexpr uint8_t WKREG_BRH
Baud rate configuration register: high byte - c0/c1 0100.
constexpr uint8_t GENA_C2EN
Channel 2 enable clock (0: disable, 1: enable)
constexpr uint8_t FSR_TFFULL
Transmitter FIFO full (0: not full, 1: full)
constexpr uint8_t LCR_PAEN
Parity enable (0: no check, 1: check)
constexpr uint8_t WKREG_FCR
FIFO Control Register - c0/c1 0110.
constexpr uint8_t WKREG_FSR
FIFO Status Register - c0/c1 1011.
constexpr uint8_t WKREG_SIFR
Serial Interrupt Flag Register (not used) - c0/c1 1000.
constexpr uint8_t SCR_TXEN
transmission control (0: enable, 1: disable)
constexpr uint8_t FSR_RFLB
Receiver FIFO Line Break (0: no LB, 1: LB)
constexpr uint8_t FSR_TFDAT
Transmitter FIFO count (0: empty, 1: not empty)
constexpr uint8_t FSR_RFPE
Receiver Parity Error (0: no PE, 1: PE)
constexpr uint8_t WKREG_GMUT
Global Master channel control register (not used) - 000010.
constexpr uint8_t LCR_STPL
Stop length (0: 1 bit, 1: 2 bits)
constexpr uint8_t WKREG_BRD
Baud rate configuration register decimal part - c0/c1 0110.
constexpr uint8_t WKREG_SIER
Serial Interrupt Enable Register (not used) - c0/c1 0111.
constexpr uint8_t LCR_PAR_EVEN
Parity even.
constexpr uint8_t FCR_RFEN
Receiver FIFO enable.
constexpr uint8_t WKREG_GIFR
Global interrupt flag register (not used) 01 0001.
constexpr uint8_t FSR_RFOE
Receiver FIFO Overflow Error (0: no OE, 1: OE)
constexpr uint8_t GENA_C3EN
Channel 3 enable clock (0: disable, 1: enable)
constexpr uint8_t WKREG_GPDAT
Global GPIO data register - 11 0001.
constexpr uint8_t FCR_TFEN
Transmitter FIFO enable.
constexpr uint8_t WKREG_RFCNT
Receiver FIFO count - c0/c1 1010.
constexpr uint8_t GRST_C1RST
Channel 1 soft reset (0: not reset, 1: reset)
constexpr uint8_t WKREG_TFI
Transmit FIFO interrupt trigger configuration (not used) - c0/c1 1000.
constexpr uint8_t SCR_RXEN
receiving control (0: enable, 1: disable)
constexpr uint8_t WKREG_LSR
Line Status Register (not used - using FIFO)
constexpr uint8_t GRST_C3RST
Channel 3 soft reset (0: not reset, 1: reset)
constexpr uint8_t WKREG_TFCNT
Transmitter FIFO Count - c0/c1 1001.
Implementation of SPI Controller mode.
constexpr uint8_t FCR_RFRST
Receiver FIFO reset.
constexpr uint8_t WKREG_SPAGE
Global Page register c0/c1 0011.
constexpr uint8_t WKREG_RFI
Receive FIFO Interrupt trigger configuration (not used) - c0/c1 0111.
constexpr uint8_t WKREG_GPDIR
Global GPIO direction register - 10 0001.
constexpr uint8_t GENA_C1EN
Channel 1 enable clock (0: disable, 1: enable)
constexpr uint8_t LCR_PAR_F1
Parity force 1.
constexpr uint8_t FSR_RFFE
Receiver FIFO Frame Error (0: no FE, 1: FE)
constexpr uint8_t GENA_C4EN
Channel 4 enable clock (0: disable, 1: enable)
constexpr uint8_t WKREG_LCR
Line Configuration Register - c0/c1 0101.