ESPHome  2025.2.0
es7243e_const.h
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1 #pragma once
2 
3 #include <cinttypes>
4 
5 namespace esphome {
6 namespace es7243e {
7 
8 // ES7243E register addresses
9 static const uint8_t ES7243E_RESET_REG00 = 0x00; // Reset control
10 static const uint8_t ES7243E_CLOCK_MGR_REG01 = 0x01; // MCLK/BCLK/ADCCLK/Analog clocks on/off
11 static const uint8_t ES7243E_CLOCK_MGR_REG02 = 0x02; // MCLK & BCLK configuration, source selection
12 
13 static const uint8_t ES7243E_CLOCK_MGR_REG03 = 0x03; // ADC Over-sample rate control
14 static const uint8_t ES7243E_CLOCK_MGR_REG04 = 0x04; // Pre-divide/Pre-multiplication
15 static const uint8_t ES7243E_CLOCK_MGR_REG05 = 0x05; // CF/DSP clock divider
16 static const uint8_t ES7243E_CLOCK_MGR_REG06 = 0x06; // BCLK divider at master mode
17 static const uint8_t ES7243E_CLOCK_MGR_REG07 = 0x07; // BCLK/LRCK/SDOUT tri-state control/LRCK divider bit 11->8
18 static const uint8_t ES7243E_CLOCK_MGR_REG08 = 0x08; // Master LRCK divider bit 7 to bit 0
19 static const uint8_t ES7243E_CLOCK_MGR_REG09 = 0x09; // SEL S1/Timer for S1
20 static const uint8_t ES7243E_SDP_REG0A = 0x0A; // SEL S3/Timer for S3
21 static const uint8_t ES7243E_SDP_REG0B = 0x0B; // SDP out mute control/I2S/left-justify case/word length/format
22 static const uint8_t ES7243E_SDP_REG0C = 0x0C; // NFS flag at slot0/LSB/TDM mode selection
23 static const uint8_t ES7243E_ADC_CTRL_REG0D = 0x0D; // data mux/pol. inv./ram clear on lrck/mclk active/gain scale up
24 static const uint8_t ES7243E_ADC_CTRL_REG0E = 0x0E; // volume control
25 static const uint8_t ES7243E_ADC_CTRL_REG0F = 0x0F; // offset freeze/auto level control/automute control/VC ramp rate
26 static const uint8_t ES7243E_ADC_CTRL_REG10 = 0x10; // automute noise gate/detection
27 static const uint8_t ES7243E_ADC_CTRL_REG11 = 0x11; // automute SDP control/out gain select
28 static const uint8_t ES7243E_ADC_CTRL_REG12 = 0x12; // controls for automute PDN_PGA/MOD/reset/digital circuit
29 static const uint8_t ES7243E_ADC_CTRL_REG13 = 0x13; // ALC rate selection/ALC target level
30 static const uint8_t ES7243E_ADC_CTRL_REG14 = 0x14; // ADCHPF stage1 coeff
31 static const uint8_t ES7243E_ADC_CTRL_REG15 = 0x15; // ADCHPF stage2 coeff
32 static const uint8_t ES7243E_ANALOG_REG16 = 0x16; // power-down/reset
33 static const uint8_t ES7243E_ANALOG_REG17 = 0x17; // VMIDSEL
34 static const uint8_t ES7243E_ANALOG_REG18 = 0x18; // ADC/ADCFL bias
35 static const uint8_t ES7243E_ANALOG_REG19 = 0x19; // PGA1/PGA2 bias
36 static const uint8_t ES7243E_ANALOG_REG1A = 0x1A; // ADCI1/ADCI23 bias
37 static const uint8_t ES7243E_ANALOG_REG1B = 0x1B; // ADCSM/ADCCM bias
38 static const uint8_t ES7243E_ANALOG_REG1C = 0x1C; // ADCVRP/ADCCPP bias
39 static const uint8_t ES7243E_ANALOG_REG1D = 0x1D; // low power bits
40 static const uint8_t ES7243E_ANALOG_REG1E = 0x1E; // low power bits
41 static const uint8_t ES7243E_ANALOG_REG1F = 0x1F; // ADC_DMIC_ON/REFSEL/VX2OFF/VX1SEL/VMIDLVL
42 static const uint8_t ES7243E_ANALOG_REG20 = 0x20; // select MIC1 as PGA1 input/PGA1 gain
43 static const uint8_t ES7243E_ANALOG_REG21 = 0x21; // select MIC2 as PGA1 input/PGA2 gain
44 static const uint8_t ES7243E_TEST_MODE_REGF7 = 0xF7;
45 static const uint8_t ES7243E_TEST_MODE_REGF8 = 0xF8;
46 static const uint8_t ES7243E_TEST_MODE_REGF9 = 0xF9;
47 static const uint8_t ES7243E_I2C_CONF_REGFA = 0xFA; // I2C signals retime/reset registers to default
48 static const uint8_t ES7243E_FLAG_REGFC = 0xFC; // CSM flag/ADC automute flag (RO)
49 static const uint8_t ES7243E_CHIP_ID1_REGFD = 0xFD; // chip ID 1, reads 0x7A (RO)
50 static const uint8_t ES7243E_CHIP_ID2_REGFE = 0xFE; // chip ID 2, reads 0x43 (RO)
51 static const uint8_t ES7243E_CHIP_VERSION_REGFF = 0xFF; // chip version, reads 0x00 (RO)
52 
53 } // namespace es7243e
54 } // namespace esphome
esphome
Implementation of SPI Controller mode.
Definition: a01nyub.cpp:7
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